The demand for ‘high performance’ in SRAM cache memories is becoming significantly important. Moreover with the advancement in technology, it becomes extremely important to meet high-speed requirements in complex circuits involving a large number of operations. In order to design high-performance system, read-modify-write (RMW) operation at higher clock frequency is desired. In RMW operation, the data is read out from the memory; a graphics controller or a CPU modifies it for subsequent rewriting operation of the modified and corrected data.
FIG. 1 presents the prior art in a conventional synchronous semiconductor memory to perform high speed RMW operation. The objective is attained in six clock cycles as highlighted below:                i.) Clock No. 1: Address signals are latched in flip-flop 101 at setup time of first clock cycle.        ii.) Clock No. 2: These address signals are decoded in a decoding circuit 102 and are inputted to a latch circuit 103 which latches the signal at the active edge of the second clock cycle.        iii.) Clock No. 3: When read command is issued from the read command circuit 112, the read control circuit 114 directs the read amplifier 107 to amplify the data outputted by the sensing amplifier 106 which in turn is selected by the column selecting signals YSWs. The data amplified by the read amplifier 107 is outputted to input/output pin DQ at the set-up timing of a third clock CLK3 outputted from the read control circuit 114. Simultaneously, for stopping a write command a signal is inputted to the write control circuit 115.        iv.) Clock No. 4: The read-data RD1 is supplied to the controller for modification and correction at the occurrence of the active edge of this clock cycle.        v.) Clock No. 5: No operation is performed at the occurrence of the active edge of this clock cycle to set the data bus in high impedance state. This high impedance state of the data bus is set to avoid a collision between the memory-driving signal and an external controller-driving signal.        vi.) Clock No. 6: during this clock cycle, rewriting in the memory after modification and correction is done.        
Hence the conventional synchronous semiconductor memory performs RMW operation in six clock cycles.
The architecture described has separate read amplifier 107 and write amplifier 109 and selectively switches the read data bus obtained from read amplifier and write data bus from write amplifier depending on whether the clock is to be utilized for read operation or write operation.
The architecture and circuitry proposed in this document aims at overcoming the above disadvantage of consuming large number of clock cycles by designing a high-speed RMW operation. In the proposed architecture, four operations are performed in a single clock cycle, namely                1. Reading from a specified location        2. Data Updation        3. Writing at same location and        4. Precharge operation        